pci.h File Reference

Routines for interfacing with the Peripheral Component Interconnect (PCI). More...

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Macros
#define	PCI_PRIMARY_BUS   0x18
	Primary bus number.
#define	PCI_SECONDARY_BUS   0x19
	Secondary bus number.
#define	PCI_HEADER_TYPE_NORMAL   0
	TODO: Document.
#define	PCI_HEADER_TYPE_BRIDGE   1
	TODO: Document.
#define	PCI_HEADER_TYPE_CARDBUS   2
	TODO: Document.
#define	PCI_TYPE_BRIDGE   0x060400
	TODO: Document.
#define	PCI_TYPE_SATA   0x010600
	TODO: Document.
#define	PCI_ADDRESS_PORT   0xCF8
	TODO: Document.
#define	PCI_VALUE_PORT   0xCFC
	TODO: Document.
#define	PCI_NONE   0xFFFF
	TODO: Document.
PCI Configuration Space
The PCI Specification defines the organization of the 256-byte. Configuration Space registers and imposes a specific template for the space. Figures 2 & 3 show the layout of the 256-byte Configuration space. All PCI compliant devices must support the Vendor ID, Device ID, Command and Status, Revision ID, Class Code and Header Type fields. Implementation of the other registers is optional, depending upon the devices functionality.
#define	PCI_VENDOR_ID   0x00
	Identifies the manufacturer of the device (16 bits). Where valid IDs are allocated by PCI-SIG (the list is here) to ensure uniqueness and 0xFFFF is an invalid value that will be returned on read accesses to Configuration Space registers of non-existent devices.
#define	PCI_DEVICE_ID   0x02
	Identifies the particular device (16 bits).
#define	PCI_COMMAND   0x04
	Provides control over a device's ability to generate and respond to PCI cycles (16 bits). Where the only functionality guaranteed to be supported by all devices is, when a 0 is written to this register, the device is disconnected from the PCI bus for all accesses except Configuration Space access.
#define	PCI_STATUS   0x06
	A register used to record status information for PCI bus related events (16 bits).
#define	PCI_REVISION_ID   0x08
	Specifies a revision identifier for a particular device (8 bits).
#define	PCI_PROG_IF   0x09
	A read-only register that specifies a register-level programming interface the device has, if it has any at all (8 bits).
#define	PCI_SUBCLASS   0x0a
	A read-only register that specifies the specific function the device performs (8 bits).
#define	PCI_CLASS   0x0b
	A read-only register that specifies the type of function the device performs (8 bits).
#define	PCI_CACHE_LINE_SIZE   0x0c
	Specifies the system cache line size in 32-bit units (8 bits). A device can limit the number of cacheline sizes it can support, if a unsupported value is written to this field, the device will behave as if a value of 0 was written.
#define	PCI_LATENCY_TIMER   0x0d
	Specifies the latency timer in units of PCI bus clocks (8 bits).
#define	PCI_HEADER_TYPE   0x0e
	Identifies the layout of the header based on the type of device it begins at byte 0x10 of the header (8 bits). A value of 0x00 specifies a general device, a value of 0x01 specifies a PCI-to-PCI bridge, and a value of 0x02 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device.
#define	PCI_BIST   0x0f
	Represents that status and allows control of devices built-in self tests (8 bits).
#define	PCI_CARDBUS_CIS   0x28
	Points to the Card Information Structure and is used by devices that share silicon between CardBus and PCI.
#define	PCI_SUBSYSTEM_VENDOR_ID   0x2c
	Points to the Subsystem Vendor ID.
#define	PCI_SUBSYSTEM_ID   0x2e
	Points to the Subsystem Device ID.
#define	PCI_ROM_ADDRESS   0x30
	Bits 31..11 are address, 10..1 reserved.
#define	PCI_CAPABILITY_LIST   0x34
	Points to a linked list of new capabilities implemented by the device. Used if bit 4 of the status register (Capabilities List bit) is set to 1. The bottom two bits are reserved and should be masked before the Pointer is used to access the Configuration Space.
#define	PCI_INTERRUPT_LINE   0x3c
	Specifies which input of the system interrupt controllers the device's interrupt pin is connected to and is implemented by any device that makes use of an interrupt pin. For the x86 architecture this register corresponds to the PIC IRQ numbers 0-15 (and not I/O APIC IRQ numbers) and a value of 0xFF defines no connection.
#define	PCI_INTERRUPT_PIN   0x3d
	Specifies which interrupt pin the device uses. Where a value of 0x01 is INTA#, 0x02 is INTB#, 0x03 is INTC#, 0x04 is INTD#, and 0x00 means the device does not use an interrupt pin.
#define	PCI_MIN_GNT   0x3e
	A read-only register that specifies the burst period length, in 1/4 microsecond units, that the device needs (assuming a 33 MHz clock rate).
#define	PCI_MAX_LAT   0x3f
	A read-only register that specifies how often the device needs access to the PCI bus (in 1/4 microsecond units).
PCI Base Addresses
Base addresses specify locations in memory or I/O space. Decoded size can be determined by writing a value of 0xffffffff to the register, and reading it back. Only 1 bits are decoded.
#define	PCI_BASE_ADDRESS_0   0x10
	Location of base address 0.
#define	PCI_BASE_ADDRESS_1   0x14
	Location of base address 1.
#define	PCI_BASE_ADDRESS_2   0x18
	Location of base address 2.
#define	PCI_BASE_ADDRESS_3   0x1c
	Location of base address 3.
#define	PCI_BASE_ADDRESS_4   0x20
	Location of base address 4.
#define	PCI_BASE_ADDRESS_5   0x24
	Location of base address 5.

Typedefs
typedef void(*	pci_scan_func_t) (uint32_t device, uint16_t vendor_id, uint16_t device_id, void *extra)
	PIC scan function.

Enumerations
enum	pci_command_bit_t {   pci_command_io_space = 0 , pci_command_memory_space = 1 , pci_command_bus_master = 2 , pci_command_special_cycles = 3 ,   pci_command_mw_ie = 4 , pci_command_vga_palette_snoop = 5 , pci_command_parity_error_response = 6 , pci_command_serr_enable = 8 ,   pci_command_fast_bb_enable = 9 , pci_command_interrupt_disable = 10 }
	Types of PCI commands. More...
enum	pci_status_bit_t {   pci_status_interrupt_status = 3 , pci_status_capabilities_list = 4 , pci_status_66_MHz_capable = 5 , pci_status_fast_bb_capable = 7 ,   pci_status_master_data_parity_error = 8 , pci_status_devsel_timing_low = 9 , pci_status_devsel_timing_high = 10 , pci_status_signalled_target_abort = 11 ,   pci_status_received_target_abort = 12 , pci_status_received_master_abort = 13 , pci_status_signalled_system_error = 14 , pci_status_detected_parity_error = 15 }
	Types of PCI status. More...

Functions
void	pci_write_8 (uint32_t device, uint32_t field, uint8_t value)
	Writes a 8bit field to the given PCI device. More...
void	pci_write_16 (uint32_t device, uint32_t field, uint16_t value)
	Writes a 16bit field to the given PCI device. More...
void	pci_write_32 (uint32_t device, uint32_t field, uint32_t value)
	Writes a 32bit field to the given PCI device. More...
uint8_t	pci_read_8 (uint32_t device, int field)
	Reads a 8bit field from the given PCI device. More...
uint16_t	pci_read_16 (uint32_t device, int field)
	Reads a 16bit field from the given PCI device. More...
uint32_t	pci_read_32 (uint32_t device, int field)
	Reads a 32bit field from the given PCI device. More...
void	pci_scan (pci_scan_func_t f, int type, void *extra)
	Scans for the given type of device. More...
void	pci_remap (void)
	PCI-to-ISA remapping.
int	pci_get_interrupt (uint32_t device)
	Retrieves the interrupt number for the given device. More...
void	pci_dump_device_data (uint32_t device, uint16_t vendorid, uint16_t deviceid)
	Dumps on DEBUG, the information about the given device. More...
void	pci_debug_scan (void)
	Prints all the devices connected to the PCI interfance.

Detailed Description

Routines for interfacing with the Peripheral Component Interconnect (PCI).

Copyright

(c) 2014-2024 This file is distributed under the MIT License. See LICENSE.md for details.